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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICC_IIDR, CPU Interface Identification Register</h1><p>The GICC_IIDR characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the implementer and revision of the CPU interface.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_IIDR are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>GICC_IIDR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="12"><a href="#fieldset_0-31_20">ProductID</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">Architecture_version</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">Revision</a></td><td class="lr" colspan="12"><a href="#fieldset_0-11_0">Implementer</a></td></tr></tbody></table><h4 id="fieldset_0-31_20">ProductID, bits [31:20]</h4><div class="field">
      <p>Product Identifier.</p>
    
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-19_16">Architecture_version, bits [19:16]</h4><div class="field">
      <p>The version of the GIC architecture that is implemented.</p>
    <table class="valuetable"><tr><th>Architecture_version</th><th>Meaning</th></tr><tr><td class="bitfield">0b0001</td><td>
          <p>GICv1.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>GICv2.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>FEAT_GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers <span class="xref">ID_PFR1</span> and <span class="xref">ID_AA64PFR0_EL1</span>.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>FEAT_GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers <span class="xref">ID_PFR1</span> and <span class="xref">ID_AA64PFR0_EL1</span>.</p>
        </td></tr></table>
      <p>Other values are reserved.</p>
    </div><h4 id="fieldset_0-15_12">Revision, bits [15:12]</h4><div class="field">
      <p>Revision number for the CPU interface.</p>
    
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-11_0">Implementer, bits [11:0]</h4><div class="field"><p>Contains the JEP106 code of the company that implemented the CPU interface.</p>
<ul>
<li>Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is <span class="hexnumber">0x4</span>.
</li><li>Bit [7] is always 0.
</li><li>Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore <span class="hexnumber">0x3B</span>.
</li></ul></div><h2>Accessing GICC_IIDR</h2><h4>GICC_IIDR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC CPU interface</td><td><span class="hexnumber">0x00FC</span></td><td>GICC_IIDR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RO</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RO</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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